ps_3_0

A programmable pixel shader is made up of a set of instructions that operate on pixel data. Registers transfer data in and out of the ALU. Additional control can be applied to modify the instruction, the results, or what data gets written out.

ps_3_0 Instructions contains a list of the available instructions.
ps_3_0 Registers lists the different types of registers used by the pixel shader ALU.
Modifiers Are used to modify the way an instruction works.
Destination Register Write Mask determines what components of the destination register get written.
Pixel Shader Source Register Modifiers alter the source register data before the instruction runs.
Source Register Swizzling gives additional control over which register components are read, copied, or written.

New Features

Add a face register. Add a position register. Color registers (v#) are now fully floating point and the texture coordinate registers (t#) have been consolidated. Input declarations take the usage names, and multiple usages are permitted for components of a given register.

Dynamic Flow Control

The device supports dynamic flow control (if bool - ps, break - ps, and break_comp - ps). The depth of nesting ranges from 0 to 24.

Number of Temporary Registers

The number of temporary registers supported is 32.

Static Flow Control Nesting Depth

The call - ps/callnz /call_pred can be nested to a maximum depth of 4. Independently, loop - ps/rep - ps instructions can be nested to a maximum depth of 4.

Arbitrary Swizzle

Arbitrary swizzle is supported. See Source Register Swizzling.

Gradient Instructions

Gradient instructions are supported. See dsx - ps, dsy - ps, and texldd - ps.

Predication

Instruction predication is supported. See Predicate Register.

Dependent Read Limit

There are no dependent read limits.

Texture Instruction Limit

There is no limit on texture instructions.

Instruction Count

Each pixel shader is allowed anywhere from 512 up to the number of slots in MaxPixelShader30InstructionSlots (not more than 32768). The number of instructions run can be much higher because of the looping support. MaxPShaderInstructionsExecuted should be at least 2^16.

Sampler Count

The number of texture samplers available is 16.

Device Caps

If ps_3_0 is supported, the following caps are supported in hardware (at a minimum):

Cap	Value
MaxTextureWidth, MaxTextureHeight	4K each
MaxTextureRepeat	8K
MaxAnisotropy	16
PixelShaderVersion	3_0
MaxPixelShader30InstructionSlots	512
The following primitive caps are set:	D3DPMISCCAPS_BLENDOP, D3DPMISCCAPS_CLIPPLANESCALEDPOINTS, D3DPMISCCAPS_CLIPTLVERTS, D3DPMISCCAPS_CULLCCW, D3DPMISCCAPS_CULLCW, D3DPMISCCAPS_CULLNONE, D3DPMISCCAPS_FOGINFVF, D3DPMISCCAPS_MASKZ
The following raster caps are set:	D3DPRASTERCAPS_MIPMAPLODBIAS, D3DPRASTERCAPS_ANISOTROPY, D3DPRASTERCAPS_COLORPERSPECTIVE, D3DPRASTERCAPS_SCISSORTEST in D3DCAPS9
Full support for depth bias including:	D3DPRASTERCAPS_SLOPESCALEDEPTHBIAS, D3DPRASTERCAPS_DEPTHBIAS
Full set of comparisons for depth and alpha test including:	All the D3DPCMPCAPS in D3DCAPS9.
Source blending modes	All blending modes are supported as a source (except D3DPBLENDCAPS_SRCALPHASAT, D3DPBLENDCAPS_BOTHSRCALPHA, and D3DPBLENDCAPS_BOTHINVSRCALPHA).
The following texture caps are supported:	D3DPTEXTURECAPS_CUBEMAP, D3DPTEXTURECAPS_MIPCUBEMAP, D3DPTEXTURECAPS_MIPMAP, D3DPTEXTURECAPS_MIPVOLUMEMAP, D3DPTEXTURECAPS_PERSPECTIVE, D3DPTEXTURECAPS_PROJECTED, D3DPTEXTURECAPS_TEXREPEATNOTSCALEDBYSIZE, D3DPTEXTURECAPS_VOLUMEMAP
The following are supported on texture filter caps, volume texture filter caps and cube texture filter caps:	D3DPTFILTERCAPS_MINFPOINT, D3DPTFILTERCAPS_MINFLINEAR, D3DPTFILTERCAPS_MINFANISOTROPIC (This is not required for VolumeTextureFilterCaps and CubeTextureFilterCaps ), D3DPTFILTERCAPS_MIPFPOINT, D3DPTFILTERCAPS_MIPFLINEAR, D3DPTFILTERCAPS_MAGFPOINT, D3DPTFILTERCAPS_MAGFLINEAR
The following texture address modes are supported at vertex and pixel stages:	D3DPTADDRESSCAPS_WRAP, D3DPTADDRESSCAPS_MIRROR, D3DPTADDRESSCAPS_CLAMP, D3DPTADDRESSCAPS_BORDER, D3DPTADDRESSCAPS_INDEPENDENTUV, D3DPTADDRESSCAPS_MIRRORONCE
All the pixel shader caps are supported.	DynamicFlowControlDepth = 24, NumTemps = 32, StaticFlowControlDepth = 4, NumInstructionSlots = 512. The following features are supported: predication, arbitrary swizzles, and gradient instructions. There is no dependent-read limit, and no limit on the mixture of texture and math instructions.
All the stencil operations are supported. This includes two sided stencil.	See D3DSTENCILOP
Device support point size per vertex	D3DFVFCAPS_PSIZE in D3DCAPS9
Non-power of 2 texture support.	Either full support or conditional non-pow-2 support; device should not have the square texture only limitation as in D3DPTEXTURECAPS_SQUAREONLY.
If the device supports multiple rendertargets, the following caps are supported:	D3DPMISCCAPS_INDEPENDENTWRITEMASKS, D3DPMISCCAPS_MRTPOSTPIXELSHADERBLENDING
If vs_3_0 is supported	MaxUserClipPlanes in D3DCAPS9 is 6