Pixel Shader Differences
Instruction Slots
Each version supports a different number of maximum instruction slots.
Version |
Maximum number of instruction slots |
ps_1_1 |
4 texture + 8 arithmetic |
ps_1_2 |
4 texture + 8 arithmetic |
ps_1_3 |
4 texture + 8 arithmetic |
ps_1_4 |
6 texture + 8 arithmetic per phase |
ps_2_0 |
32 texture + 64 arithmetic |
ps_2_x |
96 minimum, and up to the number of slots in D3DCAPS9.D3DPSHADERCAPS2_0.NumInstructionSlots. See D3DPSHADERCAPS2_0. |
ps_3_0 |
512 minimum, and up to the number of slots in D3DCAPS9.MaxPixelShader30InstructionSlots. See D3DPSHADERCAPS2_0. |
For information about the limitations of software shaders, see Software Shaders.
Flow Control Nesting Limits
ps_1_x Features
New instructions:
See ps_1_1, ps_1_2, ps_1_3, ps_1_4 Instructions.
New registers:
See ps_1_1__ps_1_2__ps_1_3__ps_1_4 Registers.
ps_2_0 Features
New features:
New instructions:
- Setup instructions - dcl - ps, dcl_samplerType - ps
- Arithmetic instructions - abs - ps, crs - ps, dp2add - ps, exp - ps, frc - ps, log - ps, m3x2 - ps, m3x3 - ps, m3x4 - ps, m4x3 - ps, m4x4 - ps, max - ps, min - ps, nrm - ps, pow - ps, rcp - ps, rsq - ps, sincos - ps
- Texture instructions - texld - ps_2_0 and up (different syntax), texldb - ps, texldp - ps
New registers:
ps_2_x Features
New features (See D3DPSHADERCAPS2_0.):
- Dynamic flow control
- Static flow control
- Nesting for dynamic and static flow control instructions
- Number of Temporary Registers (r#) increased
- Arbitrary source swizzle
- Gradient instructions
- Predication
- No dependent texture read limit
- No texture instruction limit
New instructions:
- Static flow control instructions - if bool - ps, call - ps, callnz bool - ps, else - ps, endif - ps, rep - ps, endrep - ps, label - ps, ret - ps
- Dynamic flow control instructions - break - ps, break_comp - ps, breakp - ps, callnz pred - ps, if_comp - ps, if pred - ps, setp_comp - ps
- Arithmetic instructions - dsx - ps, dsy - ps
- Texture instruction - texldd - ps
New registers:
ps_3_0 Features
New features:
- Consolidated 10 Input Registers (v#)
- Indexable Constant Float Registers (c#) with the Loop Counter Register (aL)
- Number of Temporary Registers (r#) increased to 32
- Number of Constant Float Registers (c#) increased to 224
New instructions:
New registers: