Vertex Shader Differences

Instruction Slots

Each version supports a differing number of maximum instruction slots.

For information about the limitations of software shaders, see Software Shaders.

Flow Control Nesting Limits

• See Flow Control Nesting Limits.

vs_1_1 Features

New instructions:

See Instructions - vs_1_1.

New registers:

See Registers - vs_1_1.

vs_2_0 Features

New features:

• Static flow control
• All four components of the Address Register (a0) are available.

New instructions:

• Setup instructions - defb - vs, defi - vs
• Arithmetic instructions - abs - vs, crs - vs, lrp - vs, mova - vs, nrm - vs, pow - vs, sgn - vs, sincos - vs
• Static flow control instructions - call - vs, callnz bool - vs, else - vs, endif - vs, endloop - vs, endrep - vs, if bool - vs, label - vs, loop - vs, rep - vs, ret - vs

New registers:

• Constant Boolean Register (b#)
• Constant Integer Register (i#)
• Loop Counter Register (aL)

vs_2_x Features

New features (D3DCAPS9.VS20Caps):

• Dynamic flow control
• Nesting for dynamic and static flow control instructions
• Number of Temporary Registers (r#) increased
• Predication

New Instructions:

• Dynamic flow control instructions - break - vs, break_comp - vs, breakp - vs, callnz pred - vs, if_comp - vs, if pred - vs, setp_comp - vs

New registers:

• Predicate Register (p0)

vs_3_0 Features

New features :

• Texture lookup
• Indexable Output Registers (o#)
• Number of Temporary Registers (r#) increased to 32

New instructions:

• Setup instruction - dcl_samplerType - vs
• Texture instruction - texldl - vs

New registers:

• Sampler (s#)