Programmable Vertex Shader Architecture

The following diagram illustrates the vertex shader architecture. The vertex shader architecture streams vertex data into the shader from the graphics pipeline, performs operations on the data using an arithmetic logic unit (ALU), and outputs the transformed vertex data to the graphics pipeline for further processing.

Registers are used for inputting data, outputting data, and to hold a temporary result. Each register holds four fixed point numbers. The vertex shader architecture defines several types of registers, each operating on a different type of data.

• v0–v15. Vertex registers are used to stream vertex data into the shader ALU. Vertex data is defined by an application and can contain any data.
• r0–r11. Temporary registers are used to hold intermediate results.
• a0. Version 1.1 supports one address register; version 1.0 does not have one. An address register can be used to provide an integer offset during the lookup of any register.
• c0–c95. Constant value registers are designed to input constant values to the shader.
• oDn, oFog, oPos, oPts, oTn. Output registers output data from the vertex shader to the graphics pipeline for further processing. The registers contain transformed position data, texture coordinates, diffuse color, and specular color.

For more information about vertex shader registers, see Registers.

For more information about the vertex shader instruction set, see the Vertex Shader Reference.