Programmable Pixel Shader Architecture

The following diagram illustrates the pixel shader architecture. This architecture uses pixel data from a series of input registers, performs operations on the data using an arithmetic logic unit (ALU), and outputs the transformed pixel data to the graphics pipeline for further processing.

ALU data input and output is done with four types of pixel shader registers:

• Color Registers - These registers stream iterated vertex color data from a vertex shader or the fixed function vertex pipeline to a pixel shader.
• Constant Registers - These registers provide user defined constants to the shader.
• Output/Temporary Registers - These registers provide temporary storage for intermediate calculations. The r0 register also provides the output of the pixel shader.
• Texture Registers - provide texture data to the pixel shader ALU. Data from a texture is sampled using both texture coordinates and the current texture stage attributes. For more information, see Pixel Shader Texture Addressing.

For ps 1.0 - 1.3, texture registers can be written to by the ALU, which means that texture registers can also be used as temporary registers to store intermediate results.

For ps 1.4, texture registers serve a different purpose, as read-only texture coordinate registers. To accomodate this, ps 1.4 also has more temporary registers than previous versions, and texture data can go directly into these temporary registers. This eliminates the need for texture registers.

Texture Addressing - uses texture coordinates to sample textures. For more information, see Pixel Shader Texture Addressing.

The Pixel Shader ALU provides arithmetic and texture addressing instructions. Arithmetic instructions preform basic mathematic operations on data, texture addressing instructions can be used to sample textures, or perturb texture coordinates. For more information about how instructions are the ALU pipeline, see the Pixel Shader ALU.