All the 8086 processors have the same base set of 16-bit registers. Some registers can be accessed as two separate 8-bit registers. In the 80386/486, most registers can also be accessed as extended 32-bit registers.
Figure 1.3 shows the registers common to all the 8086-based processors. Each register has its own special uses and limitations.
The 80386/486 processors use the same 8-bit and 16-bit registers that the rest of the 8086 family uses. All of these registers can be further extended to 32 bits, except segment registers, which always occupy 16 bits. The extended register names begin with the letter “E.” For example, the 32-bit extension of AX is EAX. The 80386/486 processors have two additional segment registers, FS and GS. Figure 1.4 shows the extended registers of the 80386/486.
At run time, all addresses are relative to one of four segment registers: CS, DS, SS, or ES. (The 80386/486 processors add two more, FS and GS.) These registers, their segments, and their purpose are listed below:
Register and Segment | Purpose | |
CS (Code Segment) | Contains processor instructions and their immediate operands. | |
DS (Data Segment) | Normally contains data allocated by the program. | |
SS (Stack Segment) | Creates stacks for use by PUSH, POP, CALLS, and RET. |
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ES (Extra Segment) | References secondary data segment. Used by string instructions. | |
FS, GS | Provides extra segments on the 80386/486. |
Summary: Operations on registers are usually faster than operations on memory locations.
The AX, DX, CX, BX, BP, DI, and SI registers are 16-bit general-purpose registers. They can be used for temporary data storage. Since the processor accesses registers more quickly than it can access memory, you can speed up execution by keeping the most frequently used data in registers.
The 8086 family of processors does not perform memory-to-memory operations. Thus, operations on more than one variable often require the data to be moved into registers.
Four of the general registers, AX, DX, CX, and BX, can be accessed either as two 8-bit registers or as a single 16-bit register. The AH, DH, CH, and BH registers represent the high-order 8 bits of the corresponding registers. Similarly, AL, DL, CL, and BL represent the low-order 8 bits of the registers. All the general registers can be extended to 32 bits on the 80386/486.
The 8086 family of processors has two additional registers whose values are changed automatically by the processor.
The SP register points to the current location within the stack segment. Pushing a value onto the stack decreases the value of SP by 2; popping from the stack increases the value of SP by 2. With 32-bit operands on 80386/486 processors, SP is increased or decreased by 4 instead of 2. Call instructions store the calling address on the stack and decrease SP accordingly; return instructions get the stored address and increase SP. SP can also be manipulated as a general-purpose register with instructions such as ADD.
Summary: Only the processor can change IP.
The IP register always contains the address of the next instruction to be executed. You cannot directly access or change the instruction pointer. However, instructions that control program flow (such as calls, jumps, loops, and interrupts) automatically change the instruction pointer.
Summary: Flags reveal the status of the processor.
The 16 bits in the flags register control the execution of certain instructions and reflect the current status of the processor. In 80386/486 processors, the flags register is extended to 32 bits. Some bits are undefined, so there are actually 9 flags for real mode, 11 flags (including a 2-bit flag) for 80286 protected mode, 13 for the 80386, and 14 for the 80486. The extended flags register of the 80386/486 is sometimes called “Eflags.”
Figure 1.5 shows the bits of the 32-bit flags register for the 80386/486. Only the lower word is used for the other 8086-family processors. The unmarked bits are reserved for processor use; do not modify them.
The nine flags common to all 8086-family processors are summarized below, starting with the low-order flags. In these descriptions, “set” means the bit value is 1, and “cleared” means the bit value is 0.
Flag | Description |
Carry | Set if an operation generates a carry to or a borrow from a destination operand. |
Parity | Set if the low-order bits of the result of an operation contain an even number of set bits. |
Auxiliary Carry | Set if an operation generates a carry to or a borrow from the low-order four bits of an operand. This flag is used for binary coded decimal (BCD) arithmetic. |
Zero | Set if the result of an operation is 0. |
Sign | Equal to the high-order bit of the result of an operation (0 is positive, 1 is negative). |
Trap | If set, the processor generates a single-step interrupt after each instruction. A debugging program can use this feature to execute a program one instruction at a time. |
Interrupt Enable | If set, interrupts are recognized and acted on as they are received. The bit can be cleared to turn off interrupt processing temporarily. |
Direction | Set to make string operations process down from high addresses to low addresses; can be cleared to make string operations process up from low addresses to high addresses. |
Overflow | Set if the result of an operation is too large or small to fit in the destination operand. |