Just as macros allow you to substitute text in a makefile, you can also substitute text within a macro itself. The substitution applies only to the current use of the macro and does not modify the original macro definition. To substitute text within a macro, use the following syntax:
$(macroname:string1=string2)
Every occurrence of string1 is replaced by string2 in the macro macroname. Do not put any spaces or tabs before the colon. Spaces that appear after the colon are interpreted as part of the string in which they occur. If string2 is a null string, all occurrences of string1 are deleted from the macroname macro.
Macro substitution is literal and case sensitive. This means that the case as well as the characters in string1 must match the target string in the macro exactly, or the substitution is not performed. This also means that string2 is substituted exactly as it is specified. Because substitution is literal, the strings cannot contain macro expansions.
Example 1
The following makefile illustrates macro substitution:
SOURCES = project.c one.c two.c
project.exe : $(SOURCES:.c=.obj)
LINK $**;
The predefined macro $** stands for the names of all the dependent files (See “Filename Macros”.) When this makefile is run, NMAKE executes the following command:
LINK project.obj one.obj two.obj;
The macro substitution does not alter the SOURCES macro definition; if it is used again elsewhere in the makefile, SOURCES has its original value as it was defined.
Example 2
If the macro OBJS is defined as
OBJS = ONE.OBJ TWO.OBJ THREE.OBJ
you can replace each space in the defined value of OBJS with a space, followed by a plus sign, followed by a newline character, by using
$(OBJS: = +^
)
The caret (^) tells NMAKE to treat the end of the line as a literal newline character. The expanded macro after substitution is:
ONE.OBJ +
TWO.OBJ +
THREE.OBJ
This example is useful for creating response files.