FWAIT Prefixes Generated for Processor Control Instructions

ID Number: Q34774

5.10 5.10a | 5.10 5.10a

MS-DOS | OS/2

buglist5.10 buglist5.10a fixlist6.00

Summary:

For a 80287 or 80387 processor, MASM should not be generating FWAIT

prefixes for processor control instructions that do not have no-wait

forms, including the following:

FLDCW, FLDENV, FRSTOR, FINCSTP, FDECSTP, FFREE, and FNOP

The following is an example of the wait incorrectly generated by MASM

for the FLDCW instruction:

.386

.387

.model small

.data

d1 dw 0

.code

fldcw d1

end

The fldcw generates the opcodes "9B D9 2D" when it should only

generate "D9 2D" without the "9B" wait.

Microsoft has confirmed this to be problem in MASM versions 5.1 and

5.1a. The problem was corrected in version 6.0.