FIX: FWAIT Prefixes Generated for Processor Control Instructions

Last reviewed: September 11, 1997
Article ID: Q34774

5.10 5.10a | 5.10 5.10a

MS-DOS     | OS/2

kbtool kbfixlist kbbuglist

The information in this article applies to:

Microsoft Macro Assembler for MS-DOS, versions 5.1 and 5.1a
Microsoft Macro Assembler for OS/2, versions 5.1 and 5.1a

SYMPTOMS

For a 80287 or 80387 processor, MASM should not be generating FWAIT prefixes for processor control instructions that do not have no-wait forms, including the following:

   FLDCW, FLDENV, FRSTOR, FINCSTP, FDECSTP, FFREE, and FNOP

STATUS

Microsoft has confirmed this to be problem in MASM versions 5.10 and 5.10a. This problem was corrected in MASM version 6.00.

MORE INFORMATION

The following is an example of the wait incorrectly generated by MASM for the FLDCW instruction. The fldcw generates the opcodes "9B D9 2D" when it should only generate "D9 2D" without the "9B" wait.

Sample Code

; Assemble options needed: none

   .386
   .387
   .model small
   .data

d1 DW 0

   .code

fldcw d1

END

Additional reference words: 5.10 buglist5.10 buglist5.10a fixlist6.00
KBCategory: kbtool kbfixlist kbbuglist
KBSubCategory: MLIss
Solution Type : kbfix

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Last reviewed: September 11, 1997
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