If a miniport manages a busmaster DMA device, it must ensure that any data passed to the NIC for sending over the network is actually present in physical memory before the NIC reads such data from this shared memory. Therefore, the miniport must call NdisFlushBuffer to force flushing of processor cache. The timing of the flush call is not critical but must be made in MiniportSend after the data is written to shared memory and before it is released to the NIC.
For example, to send a packet on the network, MiniportSendPackets usually gives a busmaster DMA NIC the physical addresses of the packet segments in shared memory, and then calls NdisFlushBuffer and NdisMUpdateSharedMemory. The call to NdisFlushBuffer specifies the WriteToDevice parameter as TRUE, meaning the direction of the transfer is from the host to the NIC. After the miniport has called NdisFlushBuffer and NdisMUpdateSharedMemory, it can release the data to the NIC, usually by writing to a NIC register.
Because cache-line tearing is not a problem for transmitted data, the miniport can flush the data without concern for cache fill size.
Miniports that manage PIO devices are guaranteed that the correct data is transferred to a NIC and therefore such miniports do not call NdisFlushBuffer.
Miniports for slave DMA NICs are guaranteed that NDIS will ensure cache coherency during DMA transfers.
It is generally preferable to allocate cached memory for transmit data, because noncached memory is a scarce system resource, so allocating a large block is not always possible. Any miniport that uses noncached memory must allocate it during driver initialization.
A miniport should always assume that buffers set up by a protocol driver are cached memory.