Intermediate driver
An NDIS driver that exports a set of MiniportXxx functions at its upper edge and a set of ProtocolXxx functions at its lower edge. This driver is binds to an underlying NDIS NIC driver and is bound to by an overlying transport driver.
The other type of intermediate driver exports a set of MiniportXxx functions at its upper edge, has a nonNDIS private interface at its lower edge, and binds to an underlying nonNDIS NIC driver.
IDT (interrupt dispatch table)
A kernel-defined call table with a platform-dependent number of first-level entries (some for DIRQL ISRs) and second-level entries for interrupt transfer routines (dependent on a first-level ISR). For symmetric multiprocessor platforms, the kernel sets up an IDT for each processor. See also multiprocessor machine.
The Windows NT Kernel reserves eight first-level entries per IDT for its own use; the remaining first-level entries can be connected to a platform-specific bus interrupt by the HAL or to a device interrupt. The kernel’s reserved entries (in low-to-high IRQL priority) are defined by the following constants:
· PASSIVE_LEVEL ¾ execute thread
· APC_LEVEL ¾ execute special Kernel APC
· DISPATCH_LEVEL ¾ dispatch (execute DPC)
· WAKE_LEVEL ¾ debugger execution
· CLOCK2_LEVEL ¾ interval-timer execution
· REQUEST_LEVEL ¾ interprocessor request
· POWER_LEVEL ¾ power failure notification
· HIGH_LEVEL ¾ machine checks or bus errors
The set of software and hardware interrupt vectors mapped to these constants is platform-dependent, but none can be connected to a driver’s interrupt object. The constants PASSIVE_LEVEL through DISPATCH_LEVEL and WAKE_LEVEL correspond to software interrupt vectors. DIRQLs for device drivers usually have hardware priority higher than DISPATCH_LEVEL but lower than CLOCK2_LEVEL.
An asynchronous hardware signal, usually indicating a peripheral device needs service, that is detected by the processor. An interrupt causes the processor to save state, to branch to a fixed location, and to resume execution at that location. See also IDT.
A kernel-mode-only, kernel-defined control object type, used to connect a hardware interrupt source (see DIRQL) and an ISR to an IDT entry, or to connect an ISR and an interrupt transfer routine (dependent on the ISR at its IRQL) to a second-level IDT entry.
Each interrupt object:
· Can be associated with a single IDT entry (and, therefore, with a single processor in a multiprocessor machine)
· Is either LevelSensitive or Latched, depending on the platform or device
· Can be one of several interrupt objects associated with a given IDT entry if and only if every interrupt object for that entry is of a single type (LevelSensitive or Latched)
For a second-level IDT entry, an ISR, such as an ISR for a bus adapter that is associated with a first-level IRQL routes the interrupt to the device-specific interrupt transfer routine for service via its entry in the IDT.
When more than one set of interrupt objects are connected to the same first-level IDT entry, the corresponding ISRs are called in the same order in which they were connected.
IPX (internet packet exchange)
An IRP is the basic I/O Manager structure used to communicate with drivers and to allow drivers to communicate with each other. A packet consists of two different parts:
1. Header, or fixed part of the packet ¾ Used by the I/O Manager to store information about the original request, such as the caller’s parameters, the address of the device object upon which the file is open, etc. It is also used by drivers the request. See also I/O status block and device object.
2. I/O stack locations ¾ Following the header is a set of I/O stack locations, one per driver in the chain of layered drivers for which the request is bound. Each stack location contains the parameters, function codes, and context used by the corresponding driver to determine what it is supposed to be doing.
A hardware line over which a peripheral device, bus controller, other processor, or the kernel signals a request for service to the microprocessor. See also interrupt.
IRQL (interrupt request level)
The hardware priority level at which a given kernel-mode routine runs, thereby “masking off” interrupts with equivalent and lower IRQL on the processor. Such a routine can be preempted by any interrupt with a higher IRQL. Also, running at IRQL DISPATCH_LEVEL or higher prevents threads (even those with the highest real-time priority level) from running on the same processor until the current kernel-mode routine lowers IRQL. However, running at raised IRQL on a given processor has no effect on the IRQL of any other processor in a symmetric multiprocessor machine. See also IDT, interrupt object, IRQ, ISR, multiprocessor machine, and priority.
ISA (industry standard architecture)
Also, a standard defining the architecture of the PC bus (a.k.a. “AT bus standard”).
ISR (interrupt service routine)
A routine whose function is to service a device when it generates an interrupt.
An Windows NT driver’s ISR executes at raised IRQL, usually at the DIRQL of the interrupt object(s) set up for its device (i.e., drivers connected to second-level IDT entries execute at the IRQL of the first-level entry they connect to). Every Windows NT driver’s ISR should execute as quickly as possible, doing only what is necessary to save sufficient state, to make the device stop generating interrupts, and to queue a DPC that completes interrupt processing at a lower IRQL. See also DPC object.