Offset | Field | |||||||||
Byte 0 | Tag Bit[7] | Tag Bits[6:3] | Tag Bits [2:0] | |||||||
Type = 0 | Small item name | Length = n bytes | ||||||||
Bytes 1 to n | Actual information |
Small Item Name | Value |
Plug and Play version number | 0x1 |
Logical device ID | 0x2 |
Compatible device ID | 0x3 |
IRQ format | 0x4 |
DMA format | 0x5 |
Start dependent Function | 0x6 |
End dependent Function | 0x7 |
I/O port descriptor | 0x8 |
Fixed location I/O port descriptor | 0x9 |
Reserved | 0xA - 0xD |
Vendor defined | 0xE |
End tag | 0xF |
Offset | Field Name | |
Byte 0 | Value = 00001010B (Type = 0, small item name = 0x1, length = 2) | |
Byte 1 | Plug and Play version number (in packed BCD format, major bits[7:4], minor bits[3:0]) Example: Version 1.0 = 0x10, Version 2.3 = 0x23, Version 2.91= 0x29 | |
Byte 2 | Vendor specific version number |
Offset | Field Name | |||||
Byte 0 | Value = 000101xxB (Type = 0, small item name = 0x2, length = (5 or 6)) | |||||
Byte 1 | Bit[7] 0 Bits[6:2] First character in compressed ASCII Bits[1:0] Second character in compressed ASCII bits[4:3] | |||||
Byte 2 | Bits[7:5] Second character in compressed ASCII bits[2:0] Bits[4:0] Third character in compressed ASCII | |||||
Byte 3 | (Vendor Assigned)
Bits[7:4] First hexadecimal digit of function number (bit 7 is msb) Bits[3:0] Second hexadecimal digit of function number (bit 3 is msb) | |||||
Byte 4 | (Vendor Assigned)
Bits[7:4] Third hexadecimal digit of function number (bit 7 is msb) Bits[3:0] Hexadecimal digit of revision level (bit 3 is msb) | |||||
Byte 5 | Flags: Bits[7:1], if set, indicate commands supported per logical device for registers in the range of 0x31 to 0x37 respectively. Bit[0], if set, indicates this logical device is capable of participating in the boot process Note: Cards that power-up active MUST have this bit set. However, if this bit is set, the card may or may not power-up active. | |||||
Byte 6 | Flags: Bit[7:0], if set, indicate commands supported per logical device for registers in the range of 0x38 to 0x3F respectively. |
Offset | Field Name | |||||
Byte 0 | Value = 00011100B (Type = 0, small item name = 0x3, length = 4) | |||||
Byte 1 | Bit[7] 0 Bits[6:2] First character in compressed ASCII Bits[1:0] Second character in compressed ASCII bits[4:3] | |||||
Byte 2 | Bits[7:5] Second character in compressed ASCII bits[2:0] Bits[4:0] Third character in compressed ASCII | |||||
Byte 3 | (Vendor Assigned)
Bits[7:4] First hexadecimal digit of function number (bit 7 is msb) Bits[3:0] Second hexadecimal digit of function number (bit 3 is msb) | |||||
Byte 4 | (Vendor Assigned)
Bits[7:4] Third hexadecimal digit of function number (bit 7 is msb) Bits[3:0] Hexadecimal digit of revision level (bit 3 is msb) |
Offset | Field Name | |
Byte 0 | Value = 0010001XB (Type = 0, small item name = 0x4, length = (2 or 3)) | |
Byte 1 | IRQ mask bits[7:0]. Bit[0] represents IRQ0, bit[1] is IRQ1, and so on. | |
Byte 2 | IRQ mask bits[15:8]. Bit[0] represents IRQ8, bit[1] is IRQ9, and so on. | |
Byte 3 | IRQ Information. Each bit, when set, indicates this device is capable of driving a certain type of interrupt. (Optional--if not included then assume ISA compatible edge sensitive, high true interrupts) Bit[7:4] Reserved and must be 0 Bit[3] Low true level sensitive Bit[2] High true level sensitive Bit[1] Low true edge sensitive Bit[0] High true edge sensitive (Must be supported for ISA compatibility) |
Offset | Field Name | |
Byte 0 | Value = 00101010B (Type = 0, small item name = 0x5, length = 2) | |
Byte 1 | DMA channel mask bits[7:0]. Bit[0] is channel 0. | |
Byte 2 | Bit[7] Reserved and must be 0
Bits[6:5] DMA channel speed supported Status 00 Indicates compatibility mode 01 Indicates Type A DMA as described in the EISA Specification 10 Indicates Type B DMA 11 Indicates Type F Bit[4] DMA word mode Status 0 DMA may not execute in count by word mode 1 DMA may execute in count by word mode Bit[3] DMA byte mode status Status 0 DMA may not execute in count by byte mode 1 DMA may execute in count by byte mode Bit[2] Logical device bus master status Status 0 Logical device is not a bus master 1 Logical device is a bus master Bits[1:0] DMA transfer type preference Status 00 8-bit only 01 8- and 16-bit 10 16-bit only 11 Reserved |
Offset | Field Name | |
Byte 0 | Value = 0011000xB (Type = 0, small item name = 0x6, length =(0 or 1)) |
Value | Definition | |
0 | Good configuration - Highest Priority and preferred configuration | |
1 | Acceptable configuration - Lower Priority but acceptable configuration | |
2 | Sub-optimal configuration - Functional configuration but not optimal | |
3 - 255 | Reserved |
Offset | Field Name | |
Byte 0 | Value = 00111000B (Type = 0, small item name = 0x7 length =0) |
Offset | Field Name | Definition |
Byte 0 | I/O port descriptor | Value = 01000111B (Type = 0, Small item name = 0x8, Length = 7) |
Byte 1 | Information | Bits[7:1] are reserved and must be 0 Bit[0], if set, indicates the logical device decodes the full 16 bit ISA address. If bit[0] is not set, this indicates the logical device only decodes ISA address bits[9:0]. |
Byte 2 | Range minimum base address bits[7:0] | Address bits[7:0] of the minimum base I/O address that the card may be configured for. |
Byte 3 | Range minimum base address bits[15:8] | Address bits[15:8] of the minimum base I/O address that the card may be configured for. |
Byte 4 | Range maximum base address bits[7:0] | Address bits[7:0] of the maximum base I/O address that the card may be configured for. |
Byte 5 | Range maximum base address bits[15:8] | Address bits[15:8] of the maximum base I/O address that the card may be configured for. |
Byte 6 | Base alignment | Alignment for minimum base address, increment in 1 byte blocks. |
Byte 7 | Range length | The number of contiguous I/O ports requested. |
Offset | Field Name | Definition |
Byte 0 | Fixed Location I/O port descriptor | Value = 01001011B (Type = 0, Small item name = 0x9, Length = 3) |
Byte 1 | Range base address bits[7:0] | Address bits[7:0] of the base I/O address that the card may be configured for. This descriptor assumes a 10 bit ISA address decode. |
Byte 2 | Range base address bits[9:8] | Address bits[9:8] of the base I/O address that the card may be configured for. This descriptor assumes a 10 bit ISA address decode. |
Byte 3 | Range length | The number of contiguous I/O ports requested. |
Offset | Field Name | |
Byte 0 | Value = 01110xxxB (Type = 0, small item name = 0xE, length = (1-7)) | |
Byte 1 to 7 | Vendor defined |
Offset | Field Name | |
Byte 0 | Value = 01111001B (Type = 0, small item name = 0xF, length = 1) | |
Byte 1 | Check sum covering all resource data after the serial identifier. This check sum is generated such that adding it to the sum of all the data bytes will produce a zero sum. |
Offset | Field Name | |
Byte 0 | Value = 1xxxxxxxB (Type = 1, Large item name = xxxxxxx) | |
Byte 1 | Length of data items bits[7:0] | |
Byte 2 | Length of data items bits[15:8] | |
Bytes 3 to n | Actual data items |
Large Item Name | Value |
Memory range descriptor | 0x1 |
Identifier string (ANSI) | 0x2 |
Identifier string (Unicode) | 0x3 |
Vendor defined | 0x4 |
32-bit memory range descriptor | 0x5 |
32-bit fixed location memory range descriptor | 0x6 |
Reserved | 0x7 - 0x7F |
Size | Field Name | Definition |
Byte | Memory range descriptor | Value = 10000001B (Type = 1, Large item name = 1) |
Byte | Length, bits[7:0] | Value = 00001001B (9) |
Byte | Length, bits[15:8] | Value = 00000000B |
Byte | Information | This field provides extra information about this memory.
Bit[7] Reserved and must be 0 Bit[6] Memory is an expansion ROM Bit[5] Memory is shadowable. Bits[4:3] Memory control. Status 00 8-bit memory only 01 16-bit memory only 10 8- and 16-bit supported. 11 Reserved Bit[2] Support type Status 1 decode supports high address 0 decode supports range length. Bit[1] Cache support type Status 1 read cacheable, write-through 0 non-cacheable. Bit[0] Write status Status 1 writeable 0 non-writeable (ROM) |
Byte | Range minimum base address bits[7:0] | Address bits[15:8] of the minimum base memory address for which the card may be configured. |
Byte | Range minimum base address bits[15:8] | Address bits[23:16] of the minimum base memory address for which the card may be configured |
Byte | Range maximum base address bits[7:0] | Address bits[15:8] of the maximum base memory address for which the card may be configured. |
Byte | Range maximum base address bits[15:8] | Address bits[23:16] of the maximum base memory address for which the card may be configured |
Byte | Base alignment bits[7:0] | This field contains the lower eight bits of the base alignment. The base alignment provides the increment for the minimum base address. (0x0000 = 64 KByte) |
Byte | Base alignment bits[15:8] | This field contains the upper eight bits of the base alignment. The base alignment provides the increment for the minimum base address. (0x0000 = 64 KByte) |
Byte | Range length bits[7:0] | This field contains the lower eight bits of the memory range length. The range length provides the length of the memory range in 256 byte blocks. |
Byte | Range length bits[15:8] | This field contains the upper eight bits of the memory range length. The range length field provides the length of the memory range in 256 byte blocks. |
Size | Field Name | Definition |
Byte | Identifier string | Value = 10000010B (Type = 1, Large item name = 2) |
Byte | Length, bits[7:0] | Lower eight bits of identifier string length |
Byte | Length, bits[15:8] | Upper eight bits of identifier string length |
N * bytes | Identifier string | Device description as an ANSI string |
Size | Field Name | Definition |
Byte | Identifier string | Value = 10000011B (Type = 1, Large item name = 3) |
Byte | Length, bits[7:0] | Lower eight bits of length of string plus four |
Byte | Length, bits[15:8] | Upper eight bits of length of string plus four |
Byte | Country identifier, bits[7:0] | To be determined |
Byte | Country identifier, bits[15:8] | To be determined |
N * bytes | Identifier string | Device description characters |
Size | Field Name | Definition |
Byte | Vendor defined | Value = 10000100B (Type = 1, Large item name = 4) |
Byte | Length, bits[7:0] | Lower eight bits of vendor defined data |
Byte | Length, bits[15:8] | Upper eight bits of vendor defined data |
N * bytes | Vendor Defined | Vendor defined data bytes |
Size | Field Name | Definition | |||||
Byte | Memory range descriptor | Value = 10000101B (Type = 1, Large item name = 5) | |||||
Byte | Length, bits[7:0] | Value = 00010001B (17) | |||||
Byte | Length, bits[15:8] | Value = 00000000B | |||||
Byte | Information | This field provides extra information about this memory.
Bit[7] Reserved and must be 0 Bit[6] Memory is an expansion ROM Bit[5] Memory is shadowable. Bits[4:3] Memory control. Status 00 8-bit memory only 01 16-bit memory only 10 8- and 16-bit supported. 11 32-bit memory only Bit[2] Support type Status 1 decode supports high address 0 decode supports range length Bit[1] Cache support type Status 1 read cacheable, write-through 0 non-cacheable. Bit[0] Write status Status 1 writeable 0 non-writeable (ROM) | |||||
Byte | Range minimum base address bits[7:0] | Address bits[7:0] of the minimum base memory address for which the card may be configured. | |||||
Byte | Range minimum base address bits[15:8] | Address bits[15:8] of the minimum base memory address for which the card may be configured | |||||
Byte | Range minimum base address bits[23:16] | Address bits[23:16] of the minimum base memory address for which the card may be configured. | |||||
Byte | Range minimum base address bits[31:24] | Address bits[31:24] of the minimum base memory address for which the card may be configured | |||||
Byte | Range maximum base address bits[7:0] | Address bits[7:0] of the maximum base memory address for which the card may be configured. | |||||
Byte | Range maximum base address bits[15:8] | Address bits[15:8] of the maximum base memory address for which the card may be configured | |||||
Byte | Range maximum base address bits[23:16] | Address bits[23:16] of the maximum base memory address for which the card may be configured. | |||||
Byte | Range maximum base address bits[31:24] | Address bits[31:24] of the maximum base memory address for which the card may be configured | |||||
Byte | Base alignment bits[7:0] | This field contains Bits[7:0] of the base alignment. The base alignment provides the increment for the minimum base address. | |||||
Byte | Base alignment bits[15:8] | This field contains Bits[15:8] of the base alignment. The base alignment provides the increment for the minimum base address. | |||||
Byte | Base alignment bits[23:16] | This field contains Bits[23:16] of the base alignment. The base alignment provides the increment for the minimum base address. | |||||
Byte | Base alignment bits[31:24] | This field contains Bits[31:24] of the base alignment. The base alignment provides the increment for the minimum base address. | |||||
Byte | Range length bits[7:0] | This field contains Bits[7:0] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. | |||||
Byte | Range length bits[15:8] | This field contains Bits[15:8] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. | |||||
Byte | Range length bits[23:16] | This field contains Bits[23:16] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. | |||||
Byte | Range length bits[31:24] | This field contains Bits[31:24] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. |
Size | Field Name | Definition |
Byte | Memory range descriptor | Value = 10000110B (Type = 1, Large item name = 6) |
Byte | Length, bits[7:0] | Value = 00001001B (9) |
Byte | Length, bits[15:8] | Value = 00000000B |
Byte | Information | This field provides extra information about this memory.
Bit[7] Reserved and must be 0 Bit[6] Memory is an expansion ROM Bit[5] Memory is shadowable. Bits[4:3] Memory control. Status 00 8-bit memory only 01 16-bit memory only 10 8- and 16-bit supported. 11 32-bit memory only Bit[2] Support type Status 1 decode supports high address 0 decode supports range length Bit[1] Cache support type Status 1 read cacheable, write-through 0 non-cacheable. Bit[0] Write status Status 1 writeable 0 non-writeable (ROM) |
Byte | Range base address bits[7:0] | Address bits[7:0] of the base memory address for which the card may be configured. |
Byte | Range base address bits[15:8] | Address bits[15:8] of the base memory address for which the card may be configured |
Byte | Range base address bits[23:16] | Address bits[23:16] of the base memory address for which the card may be configured. |
Byte | Range base address bits[31:24] | Address bits[31:24] of the base memory address for which the card may be configured |
Byte | Range length bits[7:0] | This field contains Bits[7:0] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. |
Byte | Range length bits[15:8] | This field contains Bits[15:8] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. |
Byte | Range length bits[23:16] | This field contains Bits[23:16] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. |
Byte | Range length bits[31:24] | This field contains Bits[31:24] of the memory range length. The range length provides the length of the memory range in 1 byte blocks. |