A.4 AT&D3 Implementation Issues

The AT&D3 command presents special problems for Plug and Play COM enumeration.

In many implementations, the hardware DTR lead is logically wired to the reset pin on the modem control processor. In this case, the modem will be reset on either the level (DTR=0) or on an edge (depending on implementation).

The useful effect is that this modem can be hard reset under PC software control. The adverse effect is that the modem controller may not be able to recover from a hard reset fast enough to respond to the enumerator, or to assert DSR if a reset clears it, and the enumerator will miss it.

There are at least two alternative implementations of &D3 that can function with the PNP COM enumerator, but they require redesign of the modem controller firmware. These are:

Modem controller firmware: (Some implementations already work this way.) If possible, this would allow the modem controller to be sufficiently initiallized to be functional when the COM enumerator begins toggling DTR. Also, this would mean that DSR wasn't automatically dropped if DTR dropped. The disadvantage is that the useful feature of &D3 would be lost, and a modem in controller firmware failure could not be reset without operator intervention.

Hybrid implementation: while ON-Hook, the modem would implement &D3 in firmware; while OFF-Hook, the modem would implement &D3 in hardware. This modem should also initialize DSR=1 within 200ms, and initialize to a software &D3 response. This would remove the capability for PC controlled hard reset while the modem is in a stable state (On-hook, idle) but retain the PC-controlled reset capability while the modem is in a vulnerable state (Off-hook, carrier on, data carrier active, possible error control and data compression engines running). Note that if the modem is Off-hook, the com port will be closed except in system failure modes, and the enumerator will not disturb the modem (see 2.1.1).

Note that a modem in recovery from a hard reset initiated while off-hook could still recognize the enumerator from the details of DTR-RTS on and off timing, and respond to the 2nd phase.