Syntax
adds $s_reg1, $s_reg2, $d_reg
adds $d_reg/$s_reg1, $s_reg2
Description
Add S_floating adds the contents of $s_reg1 or $d_reg to the contents of $s_reg2 and places the result in $d_reg. When the sum of two operands is exactly 0, the sum has a positive sign for all rounding modes except round toward minus infinity (-¥). For that rounding mode, the sum has a negative sign.
Qualifiers
The following table describes the qualifiers for the adds instructions:
| Instruction | Qualifier description |
| no qualifier | IEEE Rounding Mode: Normal rounding |
| IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled | |
| addsc | IEEE Rounding Mode: Chopped |
| addsm | IEEE Rounding Mode: Minus infinity |
| addsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11) |
| addsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled |
| addsuc | IEEE Trap Mode: Underflow enabled |
| IEEE Rounding Mode: Chopped | |
| addsum | Combined meanings of addsu and addsm |
| addsud | Combined meanings of addsu and addsd |
| addssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled |
| addssuc | Combined meanings of addss, addsu, and addsc |
| addssum | Combined meanings of addss, addsu, and addsm |
| addssud | Combined meanings of addss, addsu, and addsd |
| addssui | IEEE Trap Mode: Software, underflow enabled, inexact enabled |
| addssuic | Combined meanings of addssui and addsc |
| addssuim | Combined meanings of addssui and addsm |