Atomic Updates (lock flags)

Alpha includes two per-processor registers associated with the load locked and store conditional instructions noted below. These instructions together provide for the atomic update of an aligned quadword or aligned longword. Refer to the Alpha Architecture Reference ManualAssociated_Documents for further information.

The code sequence below illustrates atomic updates. This load-locked/store-conditional paradigm may be used whenever an atomic update of a shared aligned quadword is desired, including getting the effect of atomic bytes writes.

try_again:
   ldq_l R1, a_quadword //Load and set flag
   stq_c R1, a_quadword //<modify register R1>
   beq R1, no_store
      :
      :
no_store:
   br try_again    //code to check for excessive iterations