Syntax
divqu $s_reg1, $s_reg2, $d_reg
divqu $d_reg/$s_reg1, $s_reg2
divqu $s_reg1, val_immed, $d_reg
divqu $d_reg/$s_reg1, val_immed
Description
Divide Quadword Unsigned computes the quotient of two unsigned 64-bit values. This instruction divides the contents of $s_reg1 by the contents of $s_reg2 or the immediate value and then puts the quotient in the destination register.
If the divisor is zero, an exception is signaled and a call_pal PAL_gentrap instruction may be issued. Overflow exceptions never occur.
Note The assembler destroys the contents of temporary registers $at, $t9, $t10, $t11, and $t12 for this instruction.