Syntax
divs $s_reg1, $s_reg2, $d_reg
divs $d_reg/$s_reg1, $s_reg2
Description
Divide S_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and place the result in $d_reg. If the divisor is 0, an error is signaled if the divide-by-zero exception is enabled.
Qualifiers
The following table describes the qualifiers for the divs instructions:
| Instruction | Qualifier description |
| no qualifier | IEEE Rounding Mode: Normal rounding |
| IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled | |
| divsc | IEEE Rounding Mode: Chopped |
| divsm | IEEE Rounding Mode: Minus infinity |
| divsd | IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11) |
| divsu | IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled |
| divsuc | IEEE Trap Mode: Underflow enabled |
| IEEE Rounding Mode: Chopped | |
| divsum | Combined meanings of divsu and divsm |
| divsud | Combined meanings of divsu and divsd |
| divssu | IEEE Trap Mode: Software, underflow enabled, inexact disabled |
| divssuc | Combined meanings of divss, divsu, and divsc |
| divssum | Combined meanings of divss, divsu, and divsm |
| divssud | Combined meanings of divss, divsu, and divsd |
| divssu | IEEE Trap Mode: Software, underflow enabled, inexact enabled |
| divssuic | Combined meanings of divssui and divsc |
| divssuim | Combined meanings of divssui and divsm |