Divide T_floating (divt)

Syntax

divt $s_reg1, $s_reg2, $d_reg

divt $d_reg/$s_reg1, $s_reg2

Description

Divide T_floating computes the quotient of two values. These instructions divide the contents of $s_reg1 or $d_reg by the contents of $s_reg2 and place the result in $d_reg. If the divisor is 0, an error is signaled if the divide-by-zero exception is enabled.

Qualifiers

The following table describes the qualifiers for the divt instructions:

Instruction Qualifier description
no qualifier IEEE Rounding Mode: Normal rounding
  IEEE Trap Mode: Imprecise, integer overflow disabled, inexact disabled
divtc IEEE Rounding Mode: Chopped
divtm IEEE Rounding Mode: Minus infinity
divtd IEEE Rounding Mode: Plus infinity (ensure that the dyn field of the FPCR is 11)
divtu IEEE Trap Mode: Imprecise, underflow enabled, inexact disabled
divtuc IEEE Trap Mode: Underflow enabled
  IEEE Rounding Mode: Chopped
divtum Combined meanings of divtu and divtm
divtud Combined meanings of divtu and divtd
divtsu IEEE Trap Mode: Software, underflow enabled, inexact disabled
divtsuc Combined meanings of divts, divtu, and divtc
divtsum Combined meanings of divts, divtu, and divtm
divtsud Combined meanings of divts, divtu, and addtd
divtsui IEEE Trap Mode: Software, underflow enabled, inexact enabled
divtsuic Combined meanings of divtsui and divtc
divtsuim Combined meanings of divtsui and divtm