The floating-point control register (FPCR) contains status and control information. It controls the arithmetic rounding mode of instructions that specify dynamic rounding (d qualifier) and gives a summary for each exception type of the exception conditions detected by the floating-point instructions. It also contains an overall summary bit indicating whether an exception occurred.
The format of the floating-point control register is as follows:
The fields of the floating-point control register have the following definitions:
| Bits | Name | Description |
| 63 | sum | Summary: records the bitwise OR of the FPCR exception bits (bits 57 to 52). |
| 62-60 | raz/ign | Read-As-Zero: ignored when written. |
| 59-58 | dyn | Dynamic Rounding Mode: indicates the current rounding mode to be used by an IEEE floating-point instruction that specifies dynamic mode ( d qualifier). The bit as follows:
00 Chopped rounding mode. 01 Minus infinity. 10 Normal rounding. 11 Plus infinity. |
| 57 | iov | Integer overflow. |
| 56 | ine | Inexact result. |
| 55 | unf | Underflow. |
| 54 | ovf | Overflow. |
| 53 | dze | Division by zero. |
| 52 | inv | Invalid operation. |
| 51-0 | raz/ign | Read-As-Zero: ignored when written. |