Syntax
srl $s_reg, $d_reg
srl $d_reg/$s_reg
srl val_immed, $d_reg
srl $s_reg1, $s_reg2, $d_reg
srl $d_reg/$s_reg1, $s_reg2
srl $s_reg1, val_immed, $d_reg
srl $d_reg/$s_reg1, val_immed
Description
Shift Right Logical shifts the contents of a register right (toward the least significant bit) and inserts zeros in the vacated bit positions. The contents of $s_reg1 specifies the value to shift, and the contents of $s_reg2 or the immediate value specifies the number of bits to shift. If $s_reg2 or the immediate value is greater than 63 or less than zero, $s_reg1 shifts by the result of the following AND operation: $s_reg2 AND 63.