An NT HAL must set up adapter objects that support DMA for a wide variety of DMA devices and types of I/O buses on different machines. For example, most ISA DMA controllers, slave devices, and busmaster devices do not have enough address lines to access the full four-gigabyte system physical address space of a 32-bit CPU. By contrast, EISA DMA devices generally have more than enough address lines to access the full system physical address space in 32-bit microprocessors. Consequently, every NT HAL provides mappings between the logical address ranges that DMA devices can access and system physical address ranges.
Each HAL uses map registers, associated with NT adapter objects, to represent its mappings of device-accessible logical address ranges to system physical address ranges. During DMA transfers, the HAL uses each map register to alias a device-accessible logical page to a page of physical memory in the CPU. In effect, map registers provide scatter/gather support for NT drivers that use DMA whether their devices have scatter/gather capabilities or not.
Figure 3.5 illustrates such a physical-to-logical address mapping for the driver of an ISA DMA device without scatter/gather capabilities.
Figure 3.5 Physical, Logical, and Virtual Address Mappings
As Figure 3.5 shows, three map registers are used to alias three paged ranges of data in system physical memory to three page-sized ranges of low-order logical addresses for an ISA DMA device. During DMA operations, the device would use logical addresses to access system memory. For a comparable EISA DMA device, three map registers would also be used for three page-sized ranges of data. However, the mapped logical address ranges would not necessarily be identical to the corresponding physical address ranges, so an EISA device would also use logical addresses to access system memory.
Note also the correspondence between a map register and a virtual-to-physical entry in the MDL shown in Figure 3.5:
·Each map register and each virtual entry in an MDL maps at most a full physical page of data for a DMA transfer operation.
·Each map register and each virtual entry in an MDL might map less than a full page of data. For example, the initial virtual entry in an MDL can map to an offset from the physical page boundary, as shown previously in Figure 3.4.
·Each map register and each virtual entry in an MDL maps, at the very least, one byte.
In IRPs requesting a read or write operation, each virtual entry in the opaque-to-drivers MDL at Irp->MdlAddress represents a page boundary in the system physical memory for a user buffer. Similarly, each additional map register needed for a single DMA transfer represents a page boundary in the device-accessible logical address range aliased to system physical memory.
On every Windows NT platform, each NT adapter object has an associated set of one or more map registers located at a platform-specific (and opaque-to-drivers) base address. From an NT driver’s point of view, the MapRegisterBase shown in Figure 3.5 is a handle for a set of map registers that could be hardware registers in a chip, in a system DMA controller, or in a busmaster adapter, or could even be HAL-created virtual registers in system memory.
However, the number of map registers available with an adapter object can vary for different devices and Windows NT platforms. For example, the HAL can make more map registers available to drivers that use system DMA on some platforms than on others because the DMA controllers in different Windows NT platforms have different capabilities.