A.3. Plug and Play Logical Device Configuration Registers

The resource assignments of Plug and Play cards is programmed through the address and command/data port in the same method used for issuing commands. The following registers define memory, I/O, interrupt and DMA resources used by Plug and Play cards. These configuration registers are all based on the current logical device selected. These configuration registers are all read/write so all current configuration information may be read from a card.

A.3.1. Memory Configuration Registers

Table A-3 provides a description of how memory resources are programmed. If the configuration software did not allocate memory for any reason, then the memory resource registers (for example, 0x40, 0x41, 0x43, and 0x44 for descriptor 0) are written with a zero value. This disables the memory range.

There are a maximum of four memory descriptors available per logical device.

Memory range length registers are defined as a mask of address bits[23:8] (or [31:0] for 32-bit memory space). If a bit in the mask is set, then this indicates that memory address bit is used in a comparator to determine an address match. If a bit is clear, this indicates that memory address bit is not used in determining an address match. For example, a logical device that requests 64 KBytes of memory would have a Range Length of:

Memory range length [23:16] = 0xFF
Memory range length [15:8] = 0x00

This indicates that address bits[23:16] are used to compare for a matching address, address bits[15:8] and bits[7:0] are not used. This 64 KByte address range must be aligned on a 64 KByte or higher boundary.

Memory upper limit registers are defined as being one byte greater than the memory resource assigned. For example, a logical device that requests 64 Kbytes of memory that is assigned at a base address of 1 Mbyte would have:

Memory base [23:16] = 0x10
Memory base [15:8] = 0x00
Memory upper limit [23:16] = 0x11
Memory upper limit [15:8] = 0x00

The memory control register, 0x42 (or 0x7A for 32-bit memory), may be implemented as a read-only register in devices that do not support programmable 8/16/32 bit operation and use only one type of memory decode. Memory registers 0x43 and 0x44 (or 0x7B - 0x7E for 32-bit memory) do not need to be supported by devices that only support a fixed length memory range that is aligned on a natural boundary.

Mixing 24-bit and 32-bit memory descriptors is not allowed. For a given card, only one type of descriptor can be used. The type of the first memory descriptor in the resource data structure will determine which set of configuration registers is used (either 0x40-0x5F, or 0x76-0xA8).

Table A-3. Memory Space Configuration

Name	Register Index	Definition
Memory base address bits[23:16] descriptor 0	0x40	Read/write value indicating the selected memory base address bits[23:16] for memory descriptor 0.
Memory base address bits[15:8] descriptor 0	0x41	Read/write value indicating the selected memory base address bits[15:8] for memory descriptor 0.
Memory control	0x42	Bit[1] specifies 8/16-bit control. This bit is set to indicate 16-bit memory, and cleared to indicate 8-bit memory. Bit[0], if cleared, indicates the next field can be used as a range length for decode (implies range length and base alignment of memory descriptor are equal). Bit[0], if set, indicates the next field is the upper limit for the address. Bit[0] is read-only.
Memory upper limit address bits[23:16] or range length bits[23:16] for descriptor 0	0x43	Read/write value indicating the selected memory high address bits[23:16] for memory descriptor 0. If bit[0] of memory control is 0, this is the range length. If bit[0] of memory control is 1, this is upper limit for memory address (equal to memory base address plus the range length allocated).
Memory upper limit address bits[15:8] or range length bits[15:8] for descriptor 0	0x44	Read/write value indicating the selected memory high address bits[15:8] for memory descriptor 0, either a memory address or a range length as described above.
Filler	0x45 - 0x47	Reserved
Memory descriptor 1	0x48 - 0x4C	Memory descriptor 1
Filler	0x4D - 0x4F	Reserved
Memory descriptor 2	0x50 - 0x54	Memory descriptor 2
Filler	0x55 - 0x57	Reserved
Memory descriptor 3	0x58 - 0x5C	Memory descriptor 3
Filler	0x5D - 0x5F	Reserved

Note These registers are read/write and always reflect the current operation of all logical devices on the Plug and Play card. If a resource is not programmable, then the configuration register bits are read-only. Any unimplemented memory configuration registers must return 0 on reads.

Table A-4. 32-bit Memory Space Configuration

Name	Register Index	Definition
32 Bit Memory base address bits[31:24] descriptor 0	0x76	Read/write value indicating the selected memory base address bits[31:24] for 32 bit memory descriptor 0.
32 Bit Memory base address bits[23:16] descriptor 0	0x77	Read/write value indicating the selected memory base address bits[23:16] for 32 bit memory descriptor 0.
32 Bit Memory base address bits[15:8] descriptor 0	0x78	Read/write value indicating the selected memory base address bits[15:8] for 32 bit memory descriptor 0.
32 Bit Memory base address bits[7:0] descriptor 0	0x79	Read/write value indicating the selected memory base address bits[7:0] for 32 bit memory descriptor 0.
32 Bit Memory Control	0x7A	Bits[7:3] Reserved and must return 0 on reads Bits[2:1] Memory control. These bits indicate 8/16/32 bit memory as follows: 00 8-bit memory 01 16-bit memory 10 Reserved 11 32-bit memory If bit[0] of memory control is 0, this is the range length. If bit[0] of memory control is 1, this is upper limit for memory address (equal to memory base address plus the range length allocated). Bit[0] is read-only.
Memory upper limit address bits[31:24] or range length bits[31:24] for descriptor 0	0x7B	Read/write value indicating the selected memory high address bits[31:24] for memory descriptor 0. If bit[0] of memory control is 0, this is the range length. If bit[0] of memory control is 1, this is upper limit for memory address (equal to memory base address plus the range length allocated).
Memory upper limit address bits[23:16] or range length bits[23:16] for descriptor 0	0x7C	Read/write value indicating the selected memory high address bits[23:16] for memory descriptor 0, either a memory address or a range length as described above.
Memory upper limit address bits[15:8] or range length bits[15:8] for descriptor 0	0x7D	Read/write value indicating the selected memory high address bits[15:8] for memory descriptor 0, either a memory address or a range length as described above.
Memory upper limit address bits[7:0] or range length bits[7:0] for descriptor 0	0x7E	Read/write value indicating the selected memory high address bits[7:0] for memory descriptor 0, either a memory address or a range length as described above.
Filler	0x7F	Reserved
32 Bit Memory descriptor 1	0x80 - 0x88	32 Bit Memory descriptor 1
Filler	0x89 - 0x8F	Reserved
32 Bit Memory descriptor 2	0x90 - 0x98	32 Bit Memory descriptor 2
Filler	0x99 - 0x9F	Reserved
32 Bit Memory descriptor 3	0xA0 - 0xA8	32 Bit Memory descriptor 3

Note These registers are read/write and always reflect the current operation of all logical devices on the Plug and Play card. If a resource is not programmable, then the configuration register bits are read-only. Any unimplemented 32-bit memory configuration registers must return 0 on reads.

A.3.2. I/O Configuration Registers

Configuration registers 0x60 - 0x6F are used for I/O range configuration. There are a maximum of eight I/O descriptors available per logical device. Writing a base address of 0x0000 will disable the I/O range.

Table A-5. I/O Space Configuration

Name	Register Index	Definition
I/O port base address bits[15:8] descriptor 0	0x60	Read/write value indicating the selected I/O lower limit address bits[15:8] for I/O descriptor 0. If a logical device indicates it only uses 10 bit decoding, then bits[15:10] do not need to be supported.
I/O port base address bits [7:0] descriptor 0	0x61	Read/write value indicating the selected I/O lower limit address bits[7:0] for I/O descriptor 0.
I/O port address descriptors [1-6]	0x62 - 0x6D	I/O base addresses for I/O descriptors 1 - 6
I/O port base address bits[15:8] descriptor 7	0x6E	Read/write value indicating the selected I/O base address bits[15:8] for I/O descriptor 7. If a logical device indicates it only uses 10 bit decoding, then bits[15:10] do not need to be supported.
I/O port base address bits[7:0] descriptor 7	0x6F	Read/write value indicating the selected I/O base address bits[7:0] for I/O descriptor 7.

Note These registers are read/write and always reflect the current operation of all logical devices on the Plug and Play card. If a resource is not programmable, then the configuration register bits are read-only. Any unimplemented I/O configuration registers must return 0 on reads.

A.3.3. Interrupt Configuration Registers

Each logical device in a Plug and Play ISA card may use up to two interrupt requests and up to two DMA channels. These can be selected by writing to the appropriate configuration register.

Table A-6. Interrupt Configuration

Name	Register Index		Definition
Interrupt request level select 0		0x70		Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt level is used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is not a valid interrupt selection and represents no interrupt selection.
Interrupt request type select 0		0x71		Read/write value indicating which type of interrupt is used for the Request Level selected above. Bit[1] : Level, 1 = high, 0 = low Bit[0] : Type, 1 = level, 0 = edge If a card only supports 1 type of interrupt, this register may be read-only.
Interrupt request level select 1		0x72		Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt level is used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is not a valid interrupt selection and represents no interrupt selection.
Interrupt request type select 1		0x73		Read/write value indicating which type of interrupt is used for the Request Level selected above. Bit[1] : Level, 1 = high, 0 = low Bit[0] : Type, 1 = level, 0 = edge

Note These registers are read/write and always reflect the current operation of all logical devices on the Plug and Play card. If a resource is not programmable, then the configuration register bits are read-only. Any unimplemented interrupt configuration registers must return 0 on reads.

A.3.4. DMA Configuration Registers

Table A-7. DMA Channel Configuration

Name		Register Index		Definition
DMA channel select 0	0x74		Read/write value indicating selected DMA channels. Bits[2:0] select which DMA channel is in use for DMA 0. Zero selects DMA channel 0, seven selects DMA channel 7. DMA channel 4, the cascade channel is used to indicate no DMA channel is active.
DMA channel select 1	0x75		Read/write value indicating selected DMA channels. Bits[2:0] select which DMA channel is in use for DMA 1. Zero selects DMA channel 0, seven selects DMA channel seven. DMA channel 4, the cascade channel is used to indicate no DMA channel is active.

Note These registers are read/write and always reflect the current operation of all logical devices on the Plug and Play card. If a resource is not programmable, then the configuration register bits are read-only. Any unimplemented DMA configuration registers must return 4 on reads.

A.3.5. Reserved and Vendor Defined Configuration Registers

Registers 0xA9 - 0xEF are reserved for future Plug and Play ISA use. Registers in the range of 0xF0 - 0xFE are vendor defined and may be used for any purpose.

Table A-8. Logical Device Configuration

Name		Register Index		Definition
Logical device configuration reserved	0xA9-0xEF		Reserved
Logical device configuration vendor defined	0xF0-0xFE		Vendor defined