Note that many audio devices have dependencies which fall outside of the normal hardware resource sharing idiom, that is, IRQ, I/O, DMA, or memory ranges. For example, FM synthesizer chips often have an internal dependency on the mixer device of the card. In this example the devices should not be treated as separate logical device even though functionally they are somewhat independent of each other.
Other considerations for how to logically group the devices of a multifunction board:
Example: An audio card that includes an FM synthesizer and a digital audio (wave) playback device both connected to a mixer device.
Although these devices are somewhat functionally independent, they still have important interconnections. There must be a way to associate the synthesizer, wave, and mixer devices with each other. If such an association cannot be made, then an application would not, for example, be able to determine which mixer device to utilize in order to alter the audio being produced by a given synthesizer device. In some cases, this association cannot be accomplished in a bus-independent manner. By grouping the resources of all the devices as a single logical device (with a single devnode) the association can be made more easily.
Example: An audio card that provides Sound Blaster compatibility. However, the device can only operate in compatibility mode or native mode, but not both simultaneously.
Such a device would typically implement two register planes (one native and a second "compatibility plane" for Sound Blaster emulation) which are connected to a single DAC/ADC. Obviously these register planes are not functionally independent, they are in fact mutually exclusive. The device should not be designed as two logical devices (one using a native PNP ID and another using the Sound Blaster PNP ID). Instead, to properly handle this case, a single devnode should be created containing all required resources including both the native registers and the Sound Blaster compatible registers. The supporting drivers must handle the hardware contention between the separate register sets at the I/O level.