/v |
Controls segment load notification messages. If this option is set, all segment load notifications will be displayed. |
386env |
Controls the size of addresses, registers, and so on when displayed. When this option is on, addresses, registers, and so on are shown in 32-bit format; otherwise, they are shown in 16-bit format. |
codebytes |
Causes code bytes to be displayed along with disassembled instructions. |
crdelay = |
Implements a delay between lines emitted to the debug terminal. Specify the number of ASCII nulls between lines (0-FFFFH). |
disaddr |
Causes addresses to be displayed with disassembled instructions. |
disline |
Causes filenames and line numbers to be displayed with disassembled instructions. |
dislwr |
Causes register and instruction names to be displayed in lowercase letters. |
int3line |
Causes the filename and line number to be displayed with int 3 instructions. |
newprompt |
Causes a double prompt when paging is enabled and a nesting level if the debugger is reentered. |
newreg |
Changes the format of the register display to the newer format accommodating 32 bit registers. |
newvec |
Controls the display format for the intercepted interrupt vectors. |
regterse |
Controls the number of registers displayed by the r (Register) command. When regterse is on, only the first three lines are displayed (instead of the normal six lines plus disassembly line). |
scrncols |
Sets the number of screen columns in the debug display. The default is 79 columns. |
scrnlines |
Sets the number of screen lines in the debug display. The default is 24 lines. |
skipint3s |
Causes the debugger to ignore inline int 3 instructions. |
symaddrs |
Causes symbol values to be displayed with the symbols. |
teftibase |
Sets the base port address for the timing card. See MSDN Library CD: Q85897, "WDEB386-Compatible Timing Card Available" |